Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize the conduction power loss it is desirable that power MOSFETs have a low specific on-resistance (RSP or R*A), which is defined as the product of the on-resistance of the MOSFET multiplied by the active die area. In order to minimize the switching loss it is desired that power MOSFETs have low input and output capacitances. The most common way to reduce the RSP is to shrink the device's unit cell and pitch increase the packing density or number of cells per unit area. However, as the cell density increases, the associated intrinsic capacitances of the device, such as the gate-to-source capacitance (Cgs), the gate-to-drain capacitance (Cgd), the total input capacitance (Ciss), and the total output capacitance (Coss), also increase. As the consequence, the switching power loss of the device will increase. Therefore, it is desirable to develop a device with the best trade-off between the conduction loss and the switching loss, leading to the lowest conduction loss and the lowest switching loss at the same time.
Currently, there are two common techniques to improve the switching performance of power MOSFETs. The first one is the trench-gated MOSFET with thick bottom oxide, as shown in FIG. 1 (U.S. Pat. No. 6,849,898). The second one is the split poly gated MOSFET structure, in which the first poly gate is electrically shorted to the source electrode (U.S. Pat. Nos. 5,998,833, 6,683,346). This is illustrated in FIG. 2.
Most recently, US Patent Publication Nos. 2008/0073707 and 2009/0206924 disclosed the further improved Power MOSFET structures to realize a very short channel region (˜0.25 μm) to further reduce the device on-resistance RSP and the gate-source capacitance as well as the gate-drain capacitance. These device structures are illustrated in FIG. 3 and FIG. 4. In addition to the increase of the channel density and the reduction of channel length for decreasing the device on-resistance, the so-called charge balance technique (U.S. Pat. Nos. 5,216,275 and 5,438,215) has been proposed to achieve a flat electric field distribution in the device drift region. Consequently, the doping concentration of the drift region can be raised and the on-resistance of the device for a given breakdown voltage can be lowered significantly.